The Background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.
Memory cells of some dynamic random access memories (DRAMs) include a field-effect transistor (FET) and a capacitor. The capacitor stores binary 1's and 0's as charged or discharged states. The capacitor is controlled by switching of the corresponding FET, which also controls reading of the data stored in the memory cell.
Demand for increased memory storage capacity has led to a substantial increase in cell density. As cell density increased, cell capacitance was decreased to maintain isolation between adjacent cells in the memory array. However, reducing cell capacitance also reduces the output of the memory cells, which makes reading more difficult.
One transistor (1T) capacitor-less DRAM cells have further reduced cell size. 1T DRAM cells use a transistor body for charge storage such that a memory state can be read through a bit line biasing a drain current. Therefore, 1T DRAM cells do not need a capacitor in each cell and density can be increased. 1T DRAM technology, however, requires silicon on insulator (SOI) wafers, which are expensive, in short supply, and incompatible with traditional bulk silicon complementary metal-oxide semiconductor (CMOS) devices.